The present invention relates to logical circuit arrays, and more particularly to an array topology for a dynamic logical circuit array, in which the AND and OR planes are folded together, with the gates of all logic cell transistors oriented in the same direction when the array is fabricated as an integrated circuit.
In the past, programmable logic arrays have been used to provide complex electronic circuitry on semiconductor chips. Typically, the circuit components, e.g. transistors, which form the programmable logic array are arranged in a grid-like manner, using horizontal "rows" and vertical "columns" for carrying various signals. One section of such programmable logic arrays uses rows to form an "AND plane". Another section uses columns to form an "OR plane".
The AND plane functions by looking at data which is present on various data columns in the array (separate from the columns which constitute the OR plane), and if the condition of all of the data columns looked at is "true", the associated AND plane row will be driven so that it is also "true". Thus, the AND function is a logical function in which the output follows the input if, and only if, all of the input signals are "true".
The OR plane of a programmable logic array looks at selected rows of the AND array, and if any one or more of the rows looked at are "true", the associated OR column will be forced "true". Thus, if any one of the inputs which the OR plane looks at is "true", i.e., the first input is true "or" the second input is true "or" the third input is true, etc., the output of the OR plane will be "true".
In addition to the AND plane and OR plane, other elements, such as memory cells, can be incorporated into a programmable logic array. With proper interconnection, the elements of a programmable logic array can be designed to perform many different functional tasks, thereby providing specialized digital processors for almost any end use imaginable.
One drawback to programmable logic arrays known in the art is that since the rows associated with the AND plane are horizontal, and the columns associated with the OR plane are vertical, the transistors associated with the AND plane are rotated 90.degree. with respect to the transistors associated with the OR plane. This presents difficulty in fabricating programmable logic arrays, in the form of integrated circuits, without wasting space on the semiconductor chip. In one attempt to save space, the AND plane and OR plane have been "folded" together, so that the transistors which provide the AND and OR functions are intermingled in one area of the array, instead of the AND plane being placed in one section of the array, with the OR plane in another section. Even in structures where the AND and OR planes have been folded, the AND and OR transistors were rotated 90.degree. with respect to one another.
It would be advantageous to provide a logical circuit array structure in which the array transistors all have their gates oriented in one direction, and do not have to be rotated by 90.degree. for the AND and OR plane connections. Such a structure would enjoy enormous space savings over prior programmable logic array designs. The present invention provides such a structure.